524,288-word x 8-bit 1/7 ? the mr27v401d is a 4mbit production programmed read-only memory (p2rom) organized as 524,288word x 8bit. the mr27v401d operates on a single +3v-3.3v power supply and is ttl compatible. since the mr27v401d operates asynchronously , external clocks are not required , making this device easy-to-use. the mr27v401d is suitable as large-capacity fixed memory for microcomputers and data terminals. it is manufactured using a cmos double silicon gate technology and is offered in 32-pin dip, 32-pin sop or 32-pin tsop packages. 1a mr27v401d description features ?524,288 word x 8bit ?single +3v-3.3v power supply ?access time 80ns access time (vcc=+3v) 70ns access time (vcc=+3.3v) ?input / output ttl compatible ?three-state output ?packages 32-pin plastic dip (dip32-p-600-2.54) (product name : MR27V401D-XXRA) 32-pin plastic sop (sop32-p-525-1.27-k) (product name : mr27v401d-xxma) 32-pin plastic tsop (tsop i 32-p-814-0.50-k) (product name : mr27v401d-xxta) semiconductor november 1999 production programmed read only memory (p2rom)
a10 2/7 pin configuration (top view) mr27v401d pin names functions a0 - a18 address input d0 - d7 data output ce output enable v cc power supply voltage oe chip enable v ss gnd dc a18 a17 a13 a8 a9 a11 d6 d5 d4 d3 a14 32 31 30 2 3 4 5 29 28 27 26 6 7 8 9 25 24 23 22 10 11 12 13 21 20 19 18 14 15 16 17 a16 a7 a6 a5 a4 a3 a2 d1 d2 1 ce a15 a12 a1 a0 d0 v ss v cc oe a10 d7 32-pin dip dc a18 a17 a13 a8 a9 a11 d6 d5 d4 d3 a14 32 31 30 2 3 4 5 29 28 27 26 6 7 8 9 25 24 23 22 10 11 12 13 21 20 19 18 14 15 16 17 a16 a7 a6 a5 a4 a3 a2 d1 d2 1 ce a15 a12 a1 a0 d0 v ss v cc oe a10 d7 32-pin sop dc a18 a17 a13 a8 a9 a11 a14 a16 a7 a6 a5 a4 a3 a2 d1 d2 ce a15 a12 a1 a0 d0 v ss v cc oe 32-pin tsop 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 d3 d5 d7 d4 d6 dc don't care * * : logical input level is ignored , however the pin is connected to internal circuit.
3/7 block diagram function table stand-by read mode ce v cc l l h * : don't care (h or l) 3.0v to 3.3v d0 - d7 d out hi-z hi-z mr27v401d oe a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 d0 ce oe ce oe address buffer row decoder column decoder memory matrix multiplexer output buffer d1 d2 d3 d4 d5 d6 d7 524,288x8-bit output disable l h * dc ** ** : don't care (h or l or open)
v cc power supply voltage 4/7 operating temperature under bias storage temperature input voltage output voltage power supply voltage power dissipation per package parameter symbol t opr unit value condition recommended operating conditions input "h" level input "l" level parameter symbol v cc unit 3.6 typ. 2.7 condition t stg v i v o v cc p d 0 to 70 -55 to 125 v -0.5 to v cc + 0.5 v -0.5 to v cc + 0.5 v -0.5 to 5 w 1.0 - relative to v ss (ta=0 to 70 c) min. max. v v cc +0.5* 2.2 - v 0.6 -0.5** - v v ih v il v cc =2.7v - 3.6v voltage is relative to vss absolute maximum ratings - - mr27v401d c c * : vcc+1.5v (max.) when pulse width of overshoot is less than 10ns. ** : -1.5v (min.) when pulse width of undershoot is less than 10ns.
-- 5/7 electrical characteristics (read operation) dc characteristics 1 dc characteristics 2 mr27v401d input leakage current output leakage current v cc power supply current (standby) v cc power supply current (read) parameter symbol unit condition (v cc =3v 0.3v, ta=0 to 70 c ) input "h" level input "l" level output "h" level output "l" level voltage is relative to vss i li 10 typ. - min. max. i lo i ccsc i ccst i cca m a - 10 - m a - 50 - m a - ce=v cc 1 - ce=v ih 20 - ma tc=80ns - - v ih v il v oh v ol v cc +0.5* 2.2 v - 0.6 -0.5** v - - 2.4 v i oh =-400 m a 0.4 v i ol =2.1ma - - - ce=v il , oe=v ih v i =0 to vcc v o =0 to vcc ma input leakage current output leakage current v cc power supply current (standby) v cc power supply current (read) parameter symbol unit condition (v cc =3.3v 0.3v, ta=0 to 70 c ) input "h" level input "l" level output "h" level output "l" level voltage is relative to vss i li 10 typ. - min. max. i lo i ccsc i ccst i cca m a - 10 - m a - 50 - m a - ce=v cc 1 - ce=v ih 25 - ma tc=70ns - - v ih v il v oh v ol v cc +0.5* 2.2 v - 0.6 -0.5** v - - 2.4 v i oh =-400 m a 0.4 - v i ol =2.1ma - - - - ce=v il , oe=v ih v i =0 to vcc v o =0 to vcc ma * : vcc+1.5v (max.) when pulse width of overshoot is less than 10ns. ** : -1.5v (min.) when pulse width of undershoot is less than 10ns. * : vcc+1.5v (max.) when pulse width of overshoot is less than 10ns. ** : -1.5v (min.) when pulse width of undershoot is less than 10ns.
output mr27v401d 6/7 800ohms 50pf 2.08v ac characteristics 1 address access time ce access time oe access time output disable time parameter symbol t acc unit - condition (v cc =3v 0.3v, ta=0 to 70 c) min. max. t ce ns ce=oe=v il - ns oe=v il 40 - ns ce=v il 30 0 ns oe=v il 25 0 ns - 0 ns t oe t oh ce=v il ce=oe=v il output hold time 0v/3v 0.8v/2.0v 50pf 0.8v/2.0v measurement conditions input signal level input timing reference level output load output timing reference level 80 80 t chz t ohz address cycle time t c 80 ns - - ac characteristics 2 0v/3v 0.8v/2.0v 50pf 0.8v/2.0v measurement conditions input signal level input timing reference level output load output timing reference level address access time ce access time oe access time output disable time parameter symbol t acc unit - condition (v cc =3.3v 0.3v, ta=0 to 70 c) min. max. t ce ns - ns 35 - ns 30 0 ns 25 0 ns - 0 ns t oe t oh output hold time 70 70 t chz t ohz address cycle time t c 70 ns - - ce=oe=v il oe=v il ce=v il oe=v il ce=v il ce=oe=v il
7/7 a0 - a18 t oh t ce t oe t acc ce oe valid data hi-z hi-z d0 - d7 timing chart (read cycle) t chz t ohz mr27v401d t c pin capacitance input parameter c in unit 8 (10) typ. - (v cc =3.3v, ta=25 c, f=1mhz) min. max. pf - v i =0v output c out 10 (12) -- v o =0v symbol condition ( ) : dip only
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